1. Field of the Invention
This invention is concerned with a dynamic semiconductor memory, and in particular relates to the use of dynamic RAM (Random Access Memory) sensing circuits.
2. Description of the Prior Art
In conventional dynamic memory (RAM) sensing circuits, as shown in FIG. 1, an arrangement is used in which barrier transistors are provided between the bit lines and sensing amplifiers. In the Figure, BL and BL are paired bit lines which are respectively connected to flip-flop nodes FF and FF of sensing amplifiers through barrier transistors 1 and 2. I/O and I/O are paired input/output lines constituting the data transfer nodes to the data input buffer and data output buffer, .phi..sub.S1 and .phi..sub.S2 are clocks for pre-sensing and main sensing respectively, .phi..sub.C is the column select line signal and .phi..sub.p is a pre-charged signal for a node .phi..sub.SA. FIG. 2 shows a prior art example of a circuit for generating a gate control signal .phi..sub.T of barrier transistors 1 and 2. FIGS. 3(a), (b), (c) and (d) are charts showing the timing of the control clocks and the variation with time of the voltages at the various nodes. At first, as shown in FIG. 3(a) and FIG. 3(c), when the precharged signal .phi..sub.p is applied to the transistor 9, the node .phi..sub.SA is coupled to V.sub.DD potential through the transistor 9, so that node .phi..sub.SA is charged up to V.sub.DD -V.sub.TH.
As shown in FIG. 3(b), before the sensing operation is commenced, signal .phi..sub.T is at a level greater than "V.sub.DD +V.sub.TH ", representing MOS transistor threshold voltage V.sub.TH added to power source voltage V.sub.DD, allowing read data on bit lines BL, BL to be transferred to respective nodes FF, FF. As shown in FIG. 3(c) and (d), bit line BL and node FF are then at potential V.sub.DD and bit line BL and node FF are a little lower than potential V.sub.DD. When the sensing operation is performed, as shown in FIG. 1 and FIG. 3(a), transistors 5 and 6 are turned ON by the rising edges of .phi..sub.S1 and .phi..sub.S2 and the potential of node .phi..sub.SA is thereby lowered. Thanks to the coupling with capacitance 11 shown in FIG. 2, potential .phi..sub.T is also temporarily lowered to a level below the pre-charge potential of the bit line, e.g. potential V.sub.DD, as shown in FIG. 3(b). This results in transistors 1 and 2 shown in FIG. 1 being turned OFF, so the effect of the parasitic capacitance of the bit lines BL and BL can be excluded from the sensing system, enabling the sensing to be of high sensitivity. Subsequently, node N1 assumes a potential of greater than "V.sub.DD +V.sub.TH " because of the coupling with capacitance 12 shown in FIG. 2, thereby turning transistor 10 ON. This results in signal .phi..sub.T recovering to source voltage V.sub.DD, and the lower bit line BL being connected to earth potential V.sub.SS through transistors 2, 4, 5 and 6.
Next, when data is transferred to the input/output lines, as shown in FIG. 1 and FIG. 3(a), the selected signal .phi..sub.C assumes a potential greater than "V.sub.DD +V.sub.TH ", and transistors 7 and 8 are turned ON, so that the I/O lines, which have already been charged up to potential V.sub.DD, and the bit lines, are put into a conductive condition. Input/output line I/O connected to the higher bit line BL, which is at V.sub.DD level, maintains V.sub.DD level, while the level of input/output line I/O connected to the lower bit line BL falls, since the charge holding in the input/output lines is redistributed between the parasitic capacitance of the input/output lines and the parasitic capacitance of the bit lines. To further increase the potential difference which this charge redistribution produces between the input/output lines, the input/output lines are presensed by connecting the lower input/output line I/O to V.sub.SS potential through transistors 8, 2, 4, 5 and 6 using the sensing circuit.
However, in the conventional circuit, as shown in FIG. 3(b), the signal .phi..sub.T at this point is V.sub.DD level, so the conductance of transistor 2 is low, so that input/output line I/O discharges only slowly. Since the input/output line presensing operation in this sensing circuit occurs at a slow rate the timing of the rise of the signal .phi..sub.I that starts the main input/output line sensing operation in this input/output line sensing circuit has to be delayed, as shown in FIG. 3(a). Thus data can not be transferred at high speed.